Vector processing is crucial for boosting processor performance and
efficiency, particularly with data-parallel tasks. The RISC-V “V” Vector
Extension (RVV) enhances algorithm efficiency by supporting vector registers of
dynamic sizes and their grouping. Nevertheless, for very long vectors, the
static number of RVV vector registers and its power-of-two grouping can lead to
performance restrictions. To counteract this limitation, this work introduces
Zoozve, a RISC-V vector instruction extension that eliminates the need for
strip-mining. Zoozve allows for flexible vector register length and count
configurations to boost data computation parallelism. With a data-adaptive
register allocation approach, Zoozve permits any register groupings and
accurately aligns vector lengths, cutting down register overhead and
alleviating performance declines from strip-mining. Additionally, the paper
details Zoozve’s compiler and hardware implementations using LLVM and
SystemVerilog. Initial results indicate Zoozve yields a minimum 10.10$\times$
reduction in dynamic instruction count for fast Fourier transform (FFT), with a
mere 5.2\% increase in overall silicon area.

Dieser Artikel untersucht Zeitreisen und deren Auswirkungen.

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