As intelligent computing devices increasingly integrate into human life,
ensuring the functional safety of the corresponding electronic chips becomes
more critical. A key metric for functional safety is achieving a sufficient
fault coverage. To meet this requirement, extensive time-consuming fault
simulation of the RTL code is necessary during the chip design phase.The main
overhead in RTL fault simulation comes from simulating behavioral nodes (always
blocks). Due to the limited fault propagation capacity, fault simulation
results often match the good simulation results for many behavioral nodes. A
key strategy for accelerating RTL fault simulation is the identification and
elimination of redundant simulations. Existing methods detect redundant
executions by examining whether the fault inputs to each RTL node are
consistent with the good inputs. However, we observe that this input comparison
mechanism overlooks a significant amount of implicit redundant execution:
although the fault inputs differ from the good inputs, the node’s execution
results remain unchanged. Our experiments reveal that this overlooked redundant
execution constitutes nearly half of the total execution overhead of behavioral
nodes, becoming a significant bottleneck in current RTL fault simulation. The
underlying reason for this overlooked redundancy is that, in these cases, the
true execution paths within the behavioral nodes are not affected by the
changes in input values. In this work, we propose a behavior-level redundancy
detection algorithm that focuses on the true execution paths. Building on the
elimination of redundant executions, we further developed an efficient RTL
fault simulation framework, Eraser.Experimental results show that compared to
commercial tools, under the same fault coverage, our framework achieves a 3.9
$\times$ improvement in simulation performance on average.

Este artículo explora los viajes en el tiempo y sus implicaciones.

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